Processor Description

Control Block

Instruction Fetch

Mode Control

Opcode Decoder

Data Block

CPU Registers

ALU

Address Generator

Data Selector

Pipeline Description

Each instruction must be fetched, decoded, and executed. This normally takes at least three cycles. The pipeline can reduce the overall time to as little as one by prefetching and deocding while executing other instructions.

The number of bytes prefetched is a function of the command currently executing in the CPU. For example, if an LD instruction is executing, another LD will only have it's opcode prefetched. The operand will not be fetched until the current LD has finished executing, due to the bus WRITE.

When a control transfer takes place, the pipeline must be flushed. All prefetched values are ignored. After the control transfer instruction executes, the pipeline must start over.

Control transfer may occur from one of the following:

Memory Modes

The eZ80 CPU can operate in either the Z80 or ADL memory mode. While in Z80 mode, the processor operates with 16-bit addresses and 16-bit CPU registers. Selection of the memory mode is controlled by the ADL mode bit. The Z80 and ADL memory modes may be refered to as "ADL modes".

Z80 MEMORY Mode, AKA non-ADL mode.

ADL MEMORY Mode

Registers and Bit Flags

eZ80 CPU Working Registers

The CPU contains two banks of working reigsters -- the main register set and the alternate register set. THe main register set contains the 8-bit accumulator register (A) and six 8-bit working registers (B, C, D, E, H, L). The six 8-bit working registers can be combined to function as the multibyte register pairs BC, DE, and HL. The 8-bit Flag register F completes the main register set.

The alternate (shadow) register set contains complements to the main registers -- (A', B', C', D', E', H', L', F'). These can be swapped with the main registers quickly using the EX and EXX instructions.

eZ80 CPU Control Register Definitions

The CPU contains several registers that control CPU operation.

eZ80 CPU Control Bits

eZ80 CPU Registers in Z80 Mode

eZ80 CPU Registers in ADL Mode

eZ80 CPU Status Indicators (Flag Register)

The Flag register (F and F') contains status information for the CPU. The bit position for each flag is indicated below.

Flag Register Bit Positions
Bit 7 6 5 4 3 2 1 0
Flag S Z X H X P/V N C

where:

Carry Flag (C)

Add/Subtract Flag (N)

Parity/Overflow Flag (P/V)

Half-Carry Flag (H)

Zero Flag (Z)

Sign Flag (S)

Memory Mode Switching

ADL Mode and Z80 Mode

The CPU can easily switch between ADL and Z80 mode. There are two types of mode changes: persistent and single-instruction. Persistent mode lasts until the mode is explicitly changed again, while single-instruction mode allows a certain instruction to operate using either addressing mode without making a persistent change.

Memory Mode Compiler Directives

These compiler directives indicate that either ADL or Z80 mode is the default memory mode for the code being assembled/compiled.

Opcode Suffixes for Memory Mode Control

Special opcode suffixes are added to the instruction set to assist with memory mode switching operations. These are combined of 2 parts. The first part, either .S or .L controls the data block while the second part, either .IS or .IL controls the control block. For example, LD HL, Mmn in .IL mode vs LD HL, mn in .IS mode

Single-Instruction Memory Mode Changes

Certain CPU instructions can be appended with the mrmory opcode suffixes .SIS, .LIL, .LIS, and .SIL to indicate that a particular memory mode should be used for this instruction only.

Example 1: LD HL, Mmn in Z80 Mode

.ASSUME ADL=0       ;Z80 mode operation is default
LD HL, 3456h        ;HL[23:0] = {00h, 3456h}.
LD HL, 123456h      ;Invalid - Z80 mode cannot load 24-bit values.

LD.SIS HL, 3456h    ;Exactly the same as LD HL, 3456h because ADL=0
                    ;.IS - fetch only 16 bits of data
                    ;.S  - force upper byte of HL to an undefined state

LD.LIL HL, 123456h  ;HL[23:0] = 123456h
                    ;.IL - fetch 24-bits of data
                    ;.L  - use all 3 bytes of HL register

LD.LIS HL, 3456h    ;HL[23:0] = {00h, 3456h}
                    ;.IS - fetch only 16 bits of data
                    ;.L  - use all 3 bytes of HL register

LD.SIL HL, 123456h  ;HL[23:0] = {00h, 3456h}
                    ;.IL - fetch 24 bits of data
                    ;.S  - force upper byte of HL to undefined because
                    ;      registers are defined to be only 16-bits

Example 2: LD HL, Mmn in ADL Mode

.ASSUME ADL=1       ;ADL mode operation is default
LD HL, 3456h        ;HL[23:0] = 003456h.
LD HL, 123456h      ;HL[23:0] = 123456h.

LD.SIS HL, 3456h    ;HL[23:0] = {00h, 3456h}
                    ;.IS - fetch only 16 bits of data
                    ;.S  - force upper byte of HL to an undefined state

LD.LIL HL, 123456h  ;HL[23:0] = 123456h
                    ;.IL - fetch 24-bits of data
                    ;.L  - use all 3 bytes of HL register

LD.LIS HL, 3456h    ;HL[23:0] = {00h, 3456h}
                    ;.IS - fetch only 16 bits of data
                    ;.L  - use all 3 bytes of HL register

LD.SIL HL, 123456h  ;HL[23:0] = {00h, 3456h}
                    ;.IL - fetch 24 bits of data
                    ;.S  - force upper byte of HL to undefined because
                    ;      registers are defined to be only 16-bits

Important Notes

While the comments in the code use the term "undefined state", the paragraphs describing them state specifically that the upper bits loaded in .IL mode are replaced with 00h. If this is true on hardware, emulators should also do this for consistency.

Memory WRITEs (and presumably READs) in .S mode will use MBASE, regardless of whether .IL or .IS are used.

Suffix Completion by Assembler

The assembler will convert partial suffixes to full suffixes based on the current memory mode.

Opcode Suffix Completion by Assembler
Partial Suffix ADL Mode Bit Full Suffix
.S 0 .SIS
.S 1 .SIL
.L 0 .LIS
.L 1 .LIL
.IS 0 .SIS
.IS 1 .LIS
.IL 0 .SIL
.IL 1 .LIL

Assembly of Opcode Suffixes

During assmelby, the opcode suffixes become prefixes in the assembled code. The processor must know what type of memory exceptions must be applied to the instruction to follow. The prefix bytes replace Z80 instructions that do not offer a useful function. If a CPU assembler encounters one of these replaced instructions, it issues a warning message and assembled it as a NOP (00h).

CPU Code Suffix to Assembled Prefix Mapping
CPU Code Suffix Prefix Byte Replaced Instruction
.SIS 40h LD B,B
.LIS 49h LD C,C
.SIL 52h LD D,D
.LIL 5Bh LD E,E

For the traditional Z80 prefix bytes (CBh, DDh, EDh, and FDh), the CPU does not allow an interrupt to occur in the time between fetching one of these prefix bytes and fetching the following instruction. The MEMORY mode prefix bytes (40h, 49h, 52h, 5Bh) must precede the traditional Z80 prefix byte.

Persistent Memory Mode Changes in ADL and Z80 Modes

The CPU can only make persistent mode switches between ADL mode and Z80 mode as part of a special control transfer instruction (CALL, JP, RST, RET, RETI, or RETN), or as part of an interrupt or trap operation. This prevents the Program Counter from making an uncontrolled jump. When the memory mode is changed in any of these ways, it remains in its new state until another of these operations changes the mode back.

CALL Mmn Instruction
User Code ADL Assembled Code Operation
CALL mn 0 CD nn nm Normal Z80 CALL
CALL Mmn 1 CD nn nm MM Normal eZ80 CALL
CALL.IS mn 0 40 CD nn mm Push 02h to SPL indicating call from Z80 mode
Procede with normal Z80 CALL
CALL.IS mn 1 49 CD nn mm Push PC[15:0] to SPS stack
Push PC[23:16] to SPL stack
Push 03h to SPL stack indicating call from ADL mode
Reset ADL mode bit to 0
Set PC[15:0] = {mm, nn}
CALL.IL Mmn 0 52 CD nn mm MM Push PC[15:0] to SPL stack
Push 02h to SPL stack indicating call from Z80 mode
Set ADL mode bit to 1
Set PC[23:0] = {MM, mm, nn}
CALL.IL Mmn 1 5B CD nn mm MM Push PC[23:0] to SPL stack
Push 03h to SPL stack indicating call from ADL mode
Procede with normal eZ80 CALL


JP Mmn Instruction
User Code ADL Assembled Code Operation
JP mn 0 C3 nn mm PC[15:0] = {mm, nn}
JP.SIS mn 0 40 C3 nn mm Equivelant to JP mn
JP.LIL Mmn 0 5B C3 nn mm MM PC[23:0] = {MM, mm, nn}
Set ADL mode bit to 1
JP.SIL Mmn 0 N/A An illegal suffix for this instruction
JP.LIS mn 0 N/A An illegal suffix for this instruction
JP Mmn 1 C3 nn mm MM PC[23:0] = {MM, mm, nn}
JP.SIS mn 1 40 C3 nn mm PC[15:0] = {mm, nn}
Reset ADL mode bit to 0
JP.LIL Mmn 1 5B C3 nn mm MM Equivelant to JP Mmn
JP.SIL Mmn 1 N/A An illegal suffix for this instruction
JP.LIS mn 1 N/A An illegal suffix for this instruction


JP (rr) Instruction
User Code ADL Assembled Code Operation
JP (rr) 0 E9 or DD/FD E9 PC[15:0] = rr[15:0]
JP.S (rr) 0 40 E9 or 40 DD/FD E9 Equivelant to JP (rr)
JP.L (rr) 0 49 E9 or 49 DD/FD E9 PC[23:0] = rr[23:0]
Set ADL mode bit to 1
JP (rr) 1 E9 or DD/FD E9 PC[23:0] = rr[23:0]
JP.S (rr) 1 52 E9 or 52 DD/FD E9 PC[15:0] = rr[15:0]
Reset ADL mode bit to 0
JP.L (rr) 1 5B E9 or 5B DD/FD E9 Equivelant to JP (rr)


RST n Instruction
User Code ADL Assembled Code Operation
RST n 0 CD nn Push PC[15:0] to SPS stack
PC[15:0] = {00h, nn}
RST n 1 CD nn Push PC[23:0] to SPL stack
PC[23:0] = {0000h, nn}
RST.S n 0 40 CD nn Push PC[15:0] to SPS stack
Push 02h to SPL stack, indicating an interrupt from Z80 mode
PC[15:0] = {00h, nn}
RST.S n 1 52 CD nn Push PC[15:0] to SPS stack
Push PC[23:16] to SPL stack
Push 03h to SPL stack, indicating an interrupt from ADL mode
Reset ADL mode bit to 0
PC[15:0] = {00h, nn}
RST.L n 0 49 CD nn Push PC[15:0] to SPL stack
Push 02h to SPL stack, indicating an interrupt from Z80 mode
Set ADL mode bit to 1
PC[23:0] = {0000h, nn}
RST.L n 1 5B CD nn Push PC[23:0] to SPL stack
Push 03h to SPL stack, indicating an interrupt from ADL mode
PC[23:0] = {0000h, nn}


RET Instruction
User Code ADL Assembled Code Operation
RET 0 C9 Pop 2-byte address from SPS to PC[15:0]
RET 1 C9 Pop 3-byte address from SPL to PC[23:0]
RET.S 0 N/A An invalid suffix. RET.L must be used in all mixed-memory mode applications
RET.S 1 N/A An invalid suffix. RET.L must be used in all mixed-memory mode applications
RET.L 0 49 C9 Pop a byte from SPL into ADL to set memory mode (03h = ADL, 02h = Z80).
if ADL mode {
    pop upper byte from SPL to PC[23:16]
    pop 2-byte LS bytes from SPS to PC[15:0]
} else Z80 mode {
    pop 2-byte address from SPS to PC[15:0]
}
RET.L 1 5B C9 Pop a byte from SPL into ADL to set memory mode (03h = ADL, 02h = Z80).
if ADL mode {
    pop 3-byte address from SPL to PC[23:0]
} else Z80 mode {
    pop 2-byte address from SPL to PC[15:0]
}


RETI acts like RET but it does RETI stuff

RETN acts like RET but it does RETN stuff

Mixed-Memory Mode Applications

The Mixed-ADL (MADL) control bit affects operations of interrupts, illegal instruction traps, and restart (RST) instructions. The MADL bit must be set to 1 while executing code that runs in both Z80 and ADL mode. It can be reset to 0 when executing code that only uses Z80 or ADL mode. The default state is 0.

Technically nothing can run exclusively in ADL mode, since the CPU defaults to Z80 mode. If a single JP.LIL instruction is used at or neat the beginning of the source code to permanently change to ADL mode, it is considered to use ADL mode exclusively.

When the MADL control bit is set to 1, the CPU pushes a byte onto the (SPL?) stack containing the current memory mode whenever an interrupt, trap, or restart occurs. This happens even if the memory mode isn't changed by the event. A 02h byte is pushed if the cpu is in Z80 mode. A 03h byte is pushed if the cpu is in ADL mode.

Additionally, when the MADL control bit is set to 1, all interrupts begin in ADL mode.

The MADL control bit is set to 1 by STMIX and reset to 0 by RSMIX.

Official MIXED MEMORY Mode Guidelines

Follow these rules when including legacy Z80 code with new ADL code.

Interrupts

Terminology

Interrupt Enable Flags (IEF1 and IEF2)

Interrupts in Mixed Memory Mode Applications

eZ80 CPU Response to a NMI

This section was just a giant table in the offical documentation, go see it yourself if you need to. It's pretty similar to how it works on the Z80, but with memory mode management added in.

eZ80 CPU Response to a Maskable Interrupt

There are three interrupt modes, set by IM 0, IM 1, and IM 2. Not all eZ80 processors support all 3.

Interrupt Mode 0

Interrupt Mode 1

Interrupt Mode 2

All three interrupt modes have accompanying tables specifying exactly what happens in different memory modes. Consult the official documentation for these tables.

Illegal Instruction Traps

When an eZ80 processor fetches an illegal instruction, it performs a TRAP operation. This operates similarly to an RST 00h instruction.

if ADL mode (ADL = 1) {
    (SPL) = PC[23:0]
    if MIXED MEMORY mode (MADL = 1) {
        (SPL) = 03h
    }
    PC[23:0] = 000000h
} else Z80 mode (ADL = 0) {
    SPS = PC[15:0]
    if MIXED MEMORY mode (MADL = 1) {
        (SPL) = 02h
    }
    PC[15:0] = 0000h
}

The memory mode suffixes (.SIS, .SIL, .LIS, and .LIL) do not gurantee illegal instruction traps, even when used with instructions which have no meaning. For example, CCF.SIS is allowed.

I/O Space

The eZ80 CPu is capable of addressing a 64 KB I/O space with 16-bit addresses using speical I/O instructions. Whenever an I/O instruction is executed, the upper byte of the 24-bit address bus is undefined.

Addressing Modes

We know everything in this section. It covers different addressing modes like